Intel's Ronler Acres facility in Hillsboro, Oregon, may be significantly ahead of schedule in deploying High NA EUV lithography and Backside Power Delivery for its 18A process.
This could enable single-pass patterning, dramatically improving manufacturing efficiency and potentially lowering chip costs.
Intel may have secured a deal with Microsoft to manufacture next-generation AI chips using the 18A process.
Why this matters: If true, this resurgence could shift the balance of power in the semiconductor industry, challenging Nvidia's AI hardware dominance and re-centering cutting-edge production in the US.
Intel's potential comeback hinges on two key technological advancements: High NA EUV lithography and Backside Power Delivery (BSPDN).
High NA EUV Lithography: This next-generation technology allows for finer patterns on silicon wafers in a single exposure, reducing complexity and costs compared to current multi-patterning techniques. ASML, the sole supplier of EUV lithography machines, confirms significant process improvements with this technology.
Backside Power Delivery (BSPDN): By moving the power delivery network to the back of the silicon wafer, BSPDN reduces electrical resistance, saves power, and improves chip performance. Intel's 18A process integrates BSPDN from the outset, potentially giving it an edge over TSMC.
The timeline is also crucial. If Intel has achieved production readiness for 18A using High NA EUV now, it's potentially one to two years ahead of market expectations, altering the competitive landscape.
Potential Microsoft Partnership: Synopsys reported a U.S. hyperscaler tape-out on a 2nm-class process, which, by process of elimination, points to Microsoft and its next-generation Maia AI accelerator being manufactured by Intel using its 18A process.
Q: What is High NA EUV lithography?
It's the next generation of extreme ultraviolet lithography that allows for finer patterns on silicon wafers in a single exposure, improving manufacturing efficiency.
Q: What is Backside Power Delivery (BSPDN)?
It's a technology that moves the power delivery network to the back of the silicon wafer, reducing electrical resistance and improving chip performance.
Q: How does Intel's 18A process compare to TSMC's N2 process?
Intel's 18A combines High NA EUV and BSPDN, while TSMC's N2 uses Low NA EUV and is expected to introduce backside power in a later variant.
Intel's 18A process, featuring High NA EUV and Backside Power Delivery, could mark a significant comeback for the company in the semiconductor industry.
This could lead to increased competition and innovation, potentially benefiting consumers with better performance and lower prices.
Keep an eye on upcoming announcements from Intel and Microsoft for further confirmation of these developments.
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